AN1014/1098 1/4 application note how to minimize the st7 power consumption by microcontroller division application team introduction the purpose of this document is to present a way of minimising the st7 power consumption for low power applications. this note is based on the st72311, but is applicable to all st7 general purpose devices. 1 application environment and configuration the st7 allows four main running modes : n standard run mode: f cpu = f osc /2. n slow mode: f cpu = f osc / 4, 8, 16 or 32. n wait mode, the cpu is stopped, the peripherals are still running. n halt mode, the oscillator is turned off. for this application note, we consider the watchdog timer (wdg) enabled; therefore, the halt mode can not be used as the halt instruction resets the microcontroller when the wdg is en- abled. the wait mode is used, associated with the slow mode optimum. this slow mode clock (f cpu ) drives the active peripherals and the cpu when it is wake-up. of course, to improve performance, the halt mode should be used. in terms of applications, users usually try to optimize the power consumption during the wait loop in the main program. in this configuration the microcontroller is mostly idle, waiting for an external event, or regularly woken-up by an internal timer event. in our case, we decided to put the st7 core in wait for interrupt, with one timer active to regularly wake up the core. this en- ables the core to refresh the wdg to avoid a watchdog reset. the clock driving the active pe- ripherals and the core when it is active corresponds to the slowest clock available. it is the os- cillator clock divided by 2 then divided by 16. so the peripherals and core clock (f cpu ) is equal to the crystal value (f osc ) divided by 32. 1
application environment and configuration 2/4 to minimize the power consumption, the microcontroller is configured as described below, but of course in the application this configuration may differ, in particular the i/o port used. n the optimum slow mode is selected with the divided external clock factor equal to 32. this clock (f cpu ) drives the active peripherals (wdg and timer b) and the core when it is active. in the miscellaneous register (miscr) sms and psm1 & psm0 bits must be set. n all i/o ports are connected to an external pull-up or pull-down to avoid leakage due to floating inputs. n the watchdog timer (wdg) is active with a maximum time-out period. the wdg control register (cr) must be loaded with the value ffh. n one 16-bit timer is used to wake-up the core at regular intervals. the timer event period must be adjusted to maximum value to allow the core to refresh the wdg and to avoid a wdg reset. the timer clock equals f cpu /4, in the control register (cr2) cc1, cc2 bits must be cleared. n the external clock is selected on the unused 16-bit timer with a continuous level on the external clock pin. in the control register (cr2) cc1, cc2 bits must be set. note : if the timer a is used to regularly wake-up the wdg, the user only has to select the external clock on timer b. the continuous level on the timer input clock is already done internally, as there is no external i/o connected to the internal timer b circuit. on the contrary, if timer b is used to wake-up the micro, the user has to select the external clock on timer a and to fix a continuous level on the external clock pin. but be aware, on timer a there is only one input capture and one output compare instead of two on timer b. n the main loop contains a wait for interrupt wfi instruction. n continuous low level on each pwm output (reset state) n the a/d converter must be switched off. in the a/d control/status register (csr), the adon bit must be cleared. n the spi and sci are unused. for the st7 software configuration, please refer to your datasheet.
3/4 some measurements on st72e311 2 some measurements on st72e311 the measurement of current (i dd ) is done directly on the v dd pin. the microcontroller is in wait mode and is configured as described above, with the wdg and one 16-bit timer active. the values given in table 2 to table 3 correspond to typical measured values. they are not max- imum or minimum values. the component values for the crystal resonator are (cf crystal/ceramic resonator figure in the st72311 datasheet, clock system paragraph): c osin = c osout = 22pf r p = 10 mohm table 1. i dd in ma at t= - 40 c table 2. i dd in ma at t= + 25 c table 3. i dd in ma at t= + 125 c 3 conclusion the tables above show that the consumption of the st7 mcus is not dependant of the tem- perature. the wait minimum mode (i.e. associated with the optimun slow mode) is the best way to minimize the power consumption during wait states. crystal in mhz \ v dd in v 4.5 5 5.5 4 0.32 0.40 0.48 8 0.48 0.59 0.71 crystal in mhz \ v dd in v 4.5 5 5.5 4 0.30 0.37 0.45 8 0.47 0.57 0.68 crystal in mhz \ v dd in v 4.5 5 5.5 4 0.30 0.36 0.43 8 0.46 0.56 0.65
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